Register Set Designerbeta

Preview: mycomponent.vhdl

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity mycomponent is
    port (signal clk : in std_logic;
          signal reset : in std_logic;
          signal avs_read : in std_logic;
          signal avs_write : in std_logic;
          signal avs_address : in std_logic_vector (0 downto 0);
          signal avs_readdata : out std_logic_vector (31 downto 0);
          signal avs_writedata : in std_logic_vector (31 downto 0);
          signal avs_waitrequest : out std_logic;
          signal version : in std_logic_vector (15 downto 0));
end;
architecture rtl of mycomponent is
    signal dnt_readdataready : std_logic;
    signal dnt_readdatareg : std_logic_vector(31 downto 0);
    signal dnt_waitrequest : std_logic;
begin
avslave: process (clk,reset)
  variable dnt_readdata : std_logic_vector(31 downto 0);
  variable dnt_writedata : std_logic_vector(31 downto 0);
begin
  if reset = '1' then
    dnt_readdatareg <= (others => '0');
    dnt_readdataready <= '0';
  elsif rising_edge(clk) then
    dnt_readdataready <= dnt_waitrequest and avs_read;
    if avs_read = '1' then
      dnt_readdata := (others => '0');
      case avs_address is
        when "0" =>
          dnt_readdata(15 downto 0)  := version;
        when others =>
      end case;
    else
      dnt_readdata := (others => '0');
    end if;
    dnt_readdatareg <= dnt_readdata;
    if avs_write = '1' then
      dnt_writedata := avs_writedata;
      case avs_address is
      when others =>
      end case;
    end if;
  end if;
end process; 

dnt_waitrequest <= avs_read and not dnt_readdataready;

avs_readdata <= dnt_readdatareg;

process (avs_address)
begin
end process;

avs_waitrequest <= dnt_waitrequest;

end;